A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

Authors

  • Rimjhim Saxena M.tech Scholar SAM college of science and technology Bhopal India
  • Kiran Sharma Asst. Professor SAM college of science and technology Bhopal India

DOI:

https://doi.org/10.24113/ojssports.v7i1.119

Abstract

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

Metrics

Metrics Loading ...

References

[1] Vijaya Shekhawat, Tripti Sharma and Krishna Gopal Sharma,” 2-Bit Magnitude Comparator using GDI Technique”, IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India.
[2] Krishnendu Dhar, Aanan Chatterjee, Sayan Chatterjee,” Design of Energy Efficient High Speed Low Power Full Subtractor Using GDI Technique”, IEEE, 2014.
[3] Gholamreza Shomalnasab and Lihong Zhang,” New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE 2014.
[4] Mohammad Shueb Romi, Naushad Alam, and M. Yusuf Yasin,” An Analytical Delay Model for CMOS Inverter-Transmission Gate Structure”, IEEE 2014.
[5] Krishnendu Dhar,” Design of a High Speed, Low Power Synchronously Clocked NOR-based JK Flip-Flop using Modified GDI Technique in 45nm Technology”, IEEE 2014.
[6] E.J. Priyanka, S. Vanitha, P.C.Rupa,” Design Of GDI Based 4-Bit Multiplier Using Low Power Adder Cells”, National Conference On VLSI And Embedded Systems 2013.
[7] Kaushik Roy, Fellow, IEEE, Saibal Mukhopadhyay, Student Member, IEEE, And Hamid Mahmoodi-Meimand,” Leakage Current Mechanisms And Leakage Reduction Techniques In Deep-Submicrometer CMOS Circuits”, IEEE, Vol. 91, No. 2, February 2013.
[8] Afshin Abdollahi, Farzan Fallah, Massoud Pedram,” Leakage Current Reduction In Sequential Circuits By Modifying The Scan Chains”, International Symposium On Quality Electronic Design (ISQED’03) 2003 IEEE.

Downloads

Published

2020-02-19

How to Cite

Saxena, R., & Sharma, K. (2020). A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay. IJOSTHE, 7(1), 4. https://doi.org/10.24113/ojssports.v7i1.119